1. Field of the Description
This Application relates generally to the field of memory arrays and, more particularly, to reducing power consumption in integrated circuits that employ embedded memory arrays.
2. Relevant Background
At the heart of modern computers and consumer electronic devices such as PCs, laptops, servers, smartphones, and tablets is one or more processing elements or central processing units (“CPUs”). These processing elements perform the processing for tasks of the computer or electronics, for example, through an operating system or other software components running on the processor. These processing elements are typically fabricated as one or more integrated circuit (“IC”) semiconductor substrates or “chips.” A single CPU may include millions or even billions of transistors on the same IC chip.
The processing capabilities of modern CPUs are increasing through advances in semiconductor processing technology that speed up the transistors as well as through use of new processing techniques that increase processing throughput. One such technique is to place multiple units that read and execute processing instructions (“cores”) on the same CPU chip. Another such technique is the use of multiple levels of cache memory used to store the most commonly accessed memory locations (e.g., data cache) and/or blocks of processor instructions (e.g., instruction cache) that provide more rapid access to data and/or instructions. One or more of the levels of instruction and/or data cache memory may be embedded within the same CPU chip as the processing core(s). This technique speeds up processing operations because it is typically faster to access an embedded memory than to access a memory implemented as a separate IC chip. Specifically, because embedded memories may be placed physically closer to the processor core(s), the timing paths between the processor core(s) and the embedded memory may be either run at a higher clock frequency and/or require fewer overall clock cycles or latency for particular memory operations. Therefore, embedded memories such as cache can speed up processing operations by reducing the time required for memory operations.
As advances in IC process technology have reduced transistor dimensions, system clock speeds of IC components such as CPUs have also increased dramatically. For example, processor cores of modern CPUs now run at speeds greater than 1.0 GHz and commonly up to 3.0 GHz and beyond. At these higher clock speeds, many data paths within the CPU become critical timing paths. Critical timing paths are generally paths between sequential elements that include routing and/or combinatorial logic that constrain the maximum operating frequency of the CPU. Timing paths that perform large computations such as integer and floating point operations may be critical timing paths because of the amount of combinatorial logic required to perform the computations. Paths with extensive routing within the CPU may also be critical timing paths because of the routing delay caused by resistance and capacitance of the routing wires. Typically, paths within instruction pipelines and arithmetic units of processing core(s) within the CPU may be critical paths. Additionally, paths between blocks of a CPU are also commonly critical paths. For example, paths between a processor core and an embedded memory block on a CPU may be critical paths.
Running ICs at higher clock speeds also increases power consumption, and many IC designs may become power limited, meaning that the maximum operational clock frequency for the IC is determined by the power budget or maximum operating temperature instead of the propagation delays within critical timing paths or other timing constraints of the IC. Clock-gating is one technique that may be used to reduce power consumption. Clock-gating refers to inserting logic elements that turn off (i.e., force to a static state) some clock signals when the states of sequential elements driven by those clocks are not changing. However, inserting clock-gating elements adds delay within the clock path through the clock-gating element. In addition, clock-gating elements also require a minimum time period between the arrival of the clock-gating signal and the clock itself to ensure proper operation. Accordingly, for some critical timing paths, there may not be enough setup time between the clock-gating signal and the clock edge to insert a clock-gating element. Accordingly, reducing power consumption without impacting system clock speed and/or access timing is increasingly important for improving overall performance of systems that include embedded memory arrays.